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CHECKING UP ISOMORPHIC INCLUSIONS OF R-EXPRESSIONS IN THE CONSTRUCTION OF A SET OF SECTIONS FOR PARALLEL LOGIC CONTROL ALGORITHMS

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In the paper a hardware-level algorithm is proposed for checking up isomorphism (r-isomorphism) of R-expression trees (sections of parallel algorithm) based upon a number of R-expression tree features. A description for the corresponding hardware (accelerator) is presented to check up isomorphism of R-expressions in linear time

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