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ALGORITHM OF RATIONAL PROCESSOR ARCHITECTURE

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The paper deals with an algorithm that makes it possible to decide on processor architecture for computational kernel. This architecture provides the maximum possible rate of the computational process. The algorithm is based on a sliding window method applied to bottlenecks - fragments of program code taking a maximum percentage of time for execution. The algorithm calculates a rational number of arithmetic-logic processor core computing channels depending on the type of supported operations. Calculation of the rational number for arithmetic and logical channels of processor architecture is performed on the code example that implements the algorithm for calculating the tesseral harmonics of the Earth gravitational field. Arithmetic operations of integer and real addition (subtraction), real multiplication, as well as the operations of calculating the values of logical predicates, were considered in the example. Calculation results revealed that for considered example, rational variant of processor architecture should include two arithmetic logic channels capable of performing these operations. The developed algorithm is feasible for application in solving the synthesis tasks for processor architectures and computing systems based on them. Maximum effect after using the algorithm results is achieved at the synthesis of computing systems that perform tasks on the basis of a consistent mathematical tool.

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