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SYNTHESIS METHOD OF DIGITAL-TO-ANALOG CONVERTER SCHEMATIC MODELS FOR INTEGRATED CIRCUITS

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Subject of Research.Parasitic parameters, which appear on layout design stage of analog schematic model, cause negative effect on analog block performance. The presence of negative effect of parasitic parameters can be the reason for block inadequacy to its technical requirements. It leads to new design of schematic model. Since there is no automatic approach for generation of schematic models, which takes into account all types of parasitic parameters, time-consuming design efforts increase. The paper presents features of automated moving  from analog behavioral models to schematic ones. It is shown that detailed analysis of different types of parasitic parameters should be performed on schematic level to eliminate them from layout. Method. A method of analog model synthesis for digital-to-analog converter (DAC) is proposed. The proposed method improves block performance by minimization of parasitic parameters and provides technology migration. Main Results. The method contains additional stages as compared to traditional design flow: generation of schematic models from behavioral models, analysis of different types of parasitic parameters and the stage of model refinement. For implementation of the generation stage the software was designed, which performs automated generation of schematic model from behavioral description. The method was used to design 12-bit DAC on 350 nm technology. Parasitic parameters were defined and eliminated to increase the block high-speed performance. Practical Relevance. The proposed method can be used for DAC design on any technology. The method allows decreasing the effect of parasitic parameters and reducing design effort. The method gives the possibility for generating several architecture variants at once. 

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