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TERNARY CODE WITH SUMMATION IN AN ASYMMETRIC NUMBER SYSTEM FOR THE SYNTHESIS OF CONTROLLABLE AND SELF-CHECKING DIGITAL SYSTEMS

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An approach to the construction of a code with the summation of the bits of information vectors in a ternary asymmetric number system is proposed. Such codes are focused on the detection of errors in information vectors and have a relatively low redundancy, which makes it possible to use them effectively in the development of traceable digital devices and systems with fault detection. The features of error detection by the presented code with summation are analyzed in comparison with the known code with summation, which implies separate control of digits equal to one and digits equal to two. It is shown that a code with direct summation of the bits of information vectors uses its control bits more efficiently than the code considered earlier; moreover, it has less redundancy. At the same time, however, the proposed code does not reveal much more errors in information vectors, which can be both compositional and monotonic and asymmetric. The above circumstances are recommended to be taken into account when synthesizing digital devices operating in ternary logic.

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