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ARCHITECTURE OF AN EDA-SYSTEM ON THE BASE OF COMPETITIVE PARALLEL PROCESSES

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An architecture is proposed for EDA-system with no unified model of analyzed device. Instead of the unified model, the system incorporates a set of elementary models with separate calculation process assigned for each of them. The calculation processes are carried out in a distributed virtual computing machine, and asynchronous message exchange between the processes is performed along the routs determined by initial system topology. The proposed approach allows to avoid the impact of nonlinearities on modeling accuracy.

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