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This article describes verifier of automata-based programs created with the tool to support automatic programming UniMod. When it is used, in contrast to the well-known verifiers, there is no need to describe the model in the input language of the verifier. Requirements for the program are written in the language of temporal logic of linear time LTL (Linear Time Logic). Using this logic verification carried out by intersection of automaton-product of the model and Byuhi automaton built to deny LTL formula.