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LOCAL MINIMIZATION OF THE BURED VIAS NUMBER IN THE PRINTED CIRCUIT TOPOLOGY

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The paper deals with an algorithm for local minimization of the bured vias number on a multilayer printed circuit board. The approach is based on the topology analysis in the vicinity of an adjacent vias pair. It considers the possibility of rerouting of wires, which impede the transfer of a specific wire on a specific layer. Cases with not adjacent vias (there is a planar contact or a branch point without a via on the path from one via to another) are reduced to the case where the vias are adjacent. Some shortcomings of consistent wire routing are analyzed. The shortcomings of methods of minimizing of the vias number based on the wire fragments transfer to another layer if the transfer is carried out without conflicts are considered too. The algorithm is implemented and applied in the Russian system of computer-aided design TopoR. Comparison results of several printed circuit boards routing are presented using the algorithm and not using it. The proposed algorithm additionally reduces the number of vias by 3 – 11% in test examples of multilayer printed circuit boards.

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